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12-Bit, 65 MSPS, Dual ADC AD15252
FEATURES
12-bit, 65 MSPS dual ADC Differential input with 100 input impedance Full-scale analog input: 296 mV p-p 170 MHz, 3 dB bandwidth SNR (-9 dBFS): 64 dBFS (70 MHz AIN), 64 dBFS (140 MHz AIN) SFDR (-9 dBFS): 77 dBFS (70 MHz AIN), 73 dBFS (140 MHz AIN) 435 mW per channel Dual parallel output buses Out-of-range indicators Independent clocks Duty cycle stabilizer Twos complement or offset binary data format
OTR_A PDWNA CLKA DATA BUS A
FUNCTIONAL BLOCK DIAGRAM
AD15252
INA LPF OEB_A DFS PDWNB CLKB
INB LPF OEB_B
DATA BUS B
05154-001
APPLICATIONS
Antijam GPS receivers Wireless and wired broadband communications Communications test equipment
OTR_B
Figure 1.
GENERAL DESCRIPTION
The AD15252 is a dual, 12-bit, 65 MSPS, analog-to-digital converter (ADC). It features a differential front-end amplification circuit followed by a sample-and-hold amplifier and multistage pipeline ADC. It is designed to operate with a 3.3 V analog supply and a 2.5 V/3.3 V digital supply. Each input is fully differential, ac-coupled, and terminated in 100 input impedances. The full-scale differential signal input range is 296 mV p-p. Two parallel, 12-bit digital output buses provide data flow from the ADCs. The digital output data is presented in either straight binary or twos complement format. Out-of-range (OTR) signals indicate an overflow condition, which can be used with the most significant bit to determine low or high overflow. Dual single-ended clock inputs control all internal conversion cycles. A duty cycle stabilizer allows wide variations in the clock duty cycle while maintaining excellent performance. The AD15252 is optimized for applications in antijam global positioning receivers and is well suited for communications applications.
PRODUCT HIGHLIGHTS
1. Dual 12-bit, 65 MSPS ADC with integrated analog signal conditioning optimized for antijam global positioning system receiver (AJ-GPS) applications. Operates from a single 3.3 V power supply and features a separate digital output driver supply to accommodate 2.5 V and 3.3 V logic families. Packaged in a space-saving 8 mm x 8 mm chip scale package ball grid array (CSP_BGA) and is specified over the industrial temperature range (-40C to +85C).
2.
3.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c) 2005 Analog Devices, Inc. All rights reserved.
AD15252 TABLE OF CONTENTS
Electrical Characteristics ................................................................. 3 Absolute Maximum Ratings............................................................ 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 8 Theory of Operation ...................................................................... 11 Analog Input ............................................................................... 11 Voltage Reference ....................................................................... 11 Clock Input and Considerations .............................................. 11 Power Dissipation and Standby Mode .................................... 11 Digital Outputs ........................................................................... 12 Timing ......................................................................................... 12 Data Format ................................................................................ 12 PCB and Evaluation Board............................................................ 13 Outline Dimensions ....................................................................... 19 Ordering Guide .......................................................................... 19
REVISION HISTORY
8/05--Revision 0: Initial Version
Rev. 0 | Page 2 of 20
AD15252 ELECTRICAL CHARACTERISTICS
AVDD = 3.3 V, DRVDD = 2.5 V, encode = 65 MSPS, CLK_A = CLK_B, AIN = -9 dBFS differential input, TA= 25C, unless otherwise noted. Table 1.
Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error MATCHING CHARACTERISTICS Offset Error Gain Error Input Referred Noise ANALOG INPUT Input Range Input Resistance (RIN) 1 Input Capacitance (CIN)1 CLOCK INPUTS High Level Input Voltage (VIH) Low Level Input Voltage (VIL) High Level Input Current (IIH) Low Level Input Current (IIL) Input Capacitance (CIN) LOGIC OUTPUTS High Level Output Voltage (VOH) Low Level Output Voltage (VOL) INTERFACE TIMING Maximum Conversion Rate Minimum Conversion Rate Clock Period (tC) Clock Width High (tCH) Clock Width Low (tCL) Clock to Data (tOD) Pipeline Delay (Latency) POWER SUPPLIES Supply Voltages AVDD DRVDD Supply Currents AVDD DRVDD Total Power Dissipation Temp Test Level Min Typ 12 Guaranteed 1.7 2.0 0.35 0.8 9 172 2.0 1.0 0.87 296 100 1.8 2.0 -10 -10 2 2.49 0.2 65 1 15.4 6.2 6.2 2 7 0.8 +10 +10 Max Unit Bits
25C 25C 25C Full Full Full Full Full Full Full Full 25C 25C Full Full Full Full Full Full Full Full Full Full Full Full Full Full
IV I I V V V V V V V IV V V IV IV IV IV V IV IV VI IV V IV IV IV V
-6 -12.5
+6 +12.5
% FSR % FSR LSB LSB ppm/C ppm/C % FSR % FSR LSB rms mV p-p pF V V A A pF V V MSPS MSPS ns ns ns ns Cycles
6
Full Full Full Full Full
IV IV VI VI VI
3.0 2.25
3.3 2.5 254 12 0.87
3.6 3.6 280 15 1.0
V V mA mA W
Rev. 0 | Page 3 of 20
AD15252
Parameter SIGNAL-TO-NOISE RATIO (SNR) fINPUT = 70 MHz fINPUT = 110 MHz fINPUT = 140 MHz SINAD fINPUT = 70 MHz fINPUT = 110 MHz fINPUT = 140 MHz THD fINPUT = 70 MHz fINPUT = 110 MHz fINPUT = 140 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) fINPUT = 70 MHz fINPUT = 110 MHz fINPUT = 140 MHz CROSSTALK
1
Temp 25C 25C 25C 25C 25C 25C Full Full Full 25C 25C 25C 25C
Test Level I V I I V I V V V I V I V
Min 62.7 62.5 62.4 61.9
Typ 64.2 64.1 64 63.9 63.7 63.3 -76 -74 -72
Max
Unit dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dB
72.7 68
77.8 75.9 73.8 -70
Input resistance and capacitance shown as differential.
Table 2. Explanation of Test Levels
Test Level I II III IV V VI Description 100% production tested. 100% production tested at 25C, and sample tested at specified temperatures. Sample tested only. Parameter is guaranteed by design and characterization testing. Parameter is a typical value only. All devices are 100% production tested at 25C, guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices.
Rev. 0 | Page 4 of 20
AD15252 ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter AVDD to AGND DRVDD to DRGND DRGND to AGND DRVDD to AVDD Analog Inputs Digital Outputs CLK Operational Case Temperature Storage Temperature Range Lead Temperature: Infrared, 15 sec Rating -0.3 V, +3.9 V -0.3 V, +3.9 V -0.3 V, +0.3 V -3.9 V, +3.9 V -0.3 V, AVDD + 0.3 V -0.3 V, DRVDD + 0.3 V -0.3 V, AVDD + 0.3 V -40C to 85C -65C to 150C 230C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 5 of 20
AD15252 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
8 7 6 5 4 3 2 1 A B C D E F G
05154-003
H
BOTTOM VIEW (Not to Scale)
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. A1 A2 H1 H2 B4 G4 C4 F4 A4 E8 A3 H3 D4 E4 C5 A5 B5 A6 B6 A7 B7 A8 C6 B8 C7 C8 E3 E7 F8 F7 G8 Mnemonic VINA VINA VINB VINB CLK_A CLK_B PDWN_A PDWN_B OTR_A OTR_B VCM_A VCM_B OEB_A OEB_B D11_A(MSB) D10_A D09_A D08_A D07_A D06_A D05_A D04_A D03_A D02_A D01_A D00_A(LSB) DFS D11_B(MSB) D10_B D09_B D08_B Description Analog Input Pin (+) for Channel A. Analog Input Pin (-) for Channel A. Analog Input Pin (+) for Channel B. Analog Input Pin (-) for Channel B. Clock Input Pin for Channel A. Clock Input Pin for Channel B. Power-Down Function Selection for Channel A (Active High). Power-Down Function Selection for Channel B (Active High). Out-of-Range Indicator for Channel A. Out-of-Range Indicator for Channel B. Channel A Common Mode. Channel B Common Mode. Output Enable for Channel A. Logic 0 enables Data Bus A; Logic 1 sets outputs to high-Z. Output Enable for Channel B. Logic 0 enables Data Bus B; Logic 1 sets outputs to high-Z. Channel A Data Output Bit 11 (MSB). Channel A Data Output Bit 10. Channel A Data Output Bit 9. Channel A Data Output Bit 8. Channel A Data Output Bit 7. Channel A Data Output Bit 6. Channel A Data Output Bit 5. Channel A Data Output Bit 4. Channel A Data Output Bit 3. Channel A Data Output Bit 2. Channel A Data Output Bit 1. Channel A Data Output Bit 0 (LSB). Data Output Format Select Bit (Logic 0 for offset binary, Logic 1 for twos complement). Channel B Data Output Bit 11 (MSB). Channel B Data Output Bit 10. Channel B Data Output Bit 9. Channel B Data Output Bit 8.
Rev. 0 | Page 6 of 20
AD15252
Pin No. F6 H8 G7 H7 G6 H6 G5 H5 C1 to C3, F1 to F3 B1 to B3, D3, G1 to G3 D6, E6 D5, E5 E1 E2 D1 D2 H4, F5, D7, D8 Mnemonic D07_B D06_B D05_B D04_B D03_B D02_B D01_B D00_B AVDD AGND DRVDD DRGND REFT REFB VREF REF_RTN DNC1 to DNC4 Description Channel B Data Output Bit 7. Channel B Data Output Bit 6. Channel B Data Output Bit 5. Channel B Data Output Bit 4. Channel B Data Output Bit 3. Channel B Data Output Bit 2. Channel B Data Output Bit 1. Channel B Data Output Bit 0 (LSB). Analog Power Supply. Analog Ground. Digital Output Driver Supply. Digital Output Ground. Differential Reference (+). Differential Reference (-). Voltage Reference. Voltage Reference Return No Connect.
Rev. 0 | Page 7 of 20
AD15252 TYPICAL PERFORMANCE CHARACTERISTICS
0 -1 -2 -3 85 90
ATTENUATION (dB)
-4 -5 -6 -7 -8 -9 -10
05154-004
80
SFDR (dBFS)
75
70
65
05154-007
-11 -12 10 100 FREQUENCY (MHz)
1000
60 -15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 INPUT AMPLITUDE (dBFS)
0
Figure 3. Gain Flatness
Figure 6. Single-Tone SFDR vs. AIN with fIN = 70 MHz
0 -0.25 -0.50
90
85
30MHz FLATNESS (dB)
-0.75
-1.25 -1.50 -1.75 -2.00 -2.25
05154-005
SFDR (dBFS)
-1.00
80
75
70
65
05154-008
-2.50 -2.75 120 125 130 135 140 145 150 155
160
60 -16
-14
-12
-10
-8
-6
-4
-2
0
FREQUENCY (MHz)
INPUT AMPLITUDE (dBFS)
Figure 4. Gain Flatness fIN =125MHz to 155 MHz
Figure 7. Single-Tone SFDR vs. AIN with fIN = 110 MHz
0 -10
90
85 -20
CROSSTALK (dBFS)
-30 -40 -50 -60 -70
80
SFDR (dBFS)
05154-006
75
70
65 -80 -90 1 10 100 FREQUENCY (MHz)
05154-009
1000
60 -16
-14
-12
-10
-8
-6
-4
-2
0
INPUT AMPLITUDE (dBFS)
Figure 5. Typical Crosstalk
Figure 8. Single-Tone SFDR vs. AIN with fIN = 140 MHz
Rev. 0 | Page 8 of 20
AD15252
85
0.4 0.3
80
0.2
SFDR/SNR (dBFS)
SFDR 75
0.1
(DNL)
0 -0.1 -0.2
70
65
SNR
05154-010
60 70 110 FREQUENCY (MHz) 140
-0.4 0 512 1024 1536 2048 CODE 2560 3072 3584
4096
Figure 9. Single-Tone SNR/SFDR vs. fIN
0.7 0.6
64.4 64.2
Figure 12. Typical DNL
64.6
0.5 0.4 0.3 0.2
SINAD (dBFS)
64.0
(INL)
0.1 0 -0.1 -0.2 -0.3 -0.4
63.8 63.6 63.4
05154-011
-0.6 -0.7 0 512 1024 1536 2048 CODE 2560 3072 3584
63.0 70 110 FREQUENCY (MHz) 140
4096
Figure 10. Single-Tone SINAD vs. fIN
Figure 13. Typical INL
-68 -70 -72 -74 -76 -78 -80
05154-012
0 -10 -20 -30
MAGNITUDE (dB)
1
-40 -50 -60 -70 -80 -90 -100
05154-023
THD (dBFS)
2
3
4
5
6
-82 -84 70 110 FREQUENCY (MHz) 140
-110 -120 -130 0 3.25 6.50
9.75 13.00 16.25 19.50 22.75 26.00 29.25 32.50 FREQUENCY (MHz)
Figure 11. Single-Tone THD vs. fIN
Figure 14. Single-Tone FFT of Channel A Digitizing fIN = 70 MHz @ -9 dBFS While Channel B Digitizes fIN = 70 MHz @ -9 dBFS
Rev. 0 | Page 9 of 20
05154-019
63.2
-0.5
05154-014
-0.3
AD15252
0 -10 -20 -30
MAGNITUDE (dB)
1
0 -10 -20 -30
1
MAGNITUDE (dB)
-40 -50 -60 -70 -80 -90 -100
05154-024
-40 -50 -60 -70 -80 -90 -100
05154-021
2 6 5 4 3
2
3
4
5
6
-110 -120 -130 0 3.25 6.50
-110 -120 -130 0 3.25 6.50
9.75 13.00 16.25 19.50 22.75 26.00 29.25 32.50 FREQUENCY (MHz)
9.75 13.00 16.25 19.50 22.75 26.00 29.25 32.50 FREQUENCY (MHz)
Figure 15. Single-Tone FFT of Channel B Digitizing fIN = 70 MHz @ -9 dBFS While Channel A Digitizes fIN = 70 MHz @ -9 dBFS
Figure 18. Single-Tone FFT of Channel A Digitizing fIN = 140 MHz @ -9 dBFS While Channel B Digitizes fIN = 140 MHz @ -9 dBFS
0 -10 -20 -30
MAGNITUDE (dB)
0 1 -10 -20 -30 MAGNITUDE (dB) -40 -50 -60 -70 -80 -90 -100
05154-025
1
-40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 3.25 6.50 3 6 4 2 5
2 6 5 4 3
-120 -130 0 3.25 6.50
9.75 13.00 16.25 19.50 22.75 26.00 29.25 32.50 FREQUENCY (MHz)
9.75 13.00 16.25 19.50 22.75 26.00 29.25 32.50 FREQUENCY (MHz)
Figure 16. Single-Tone FFT of Channel A Digitizing fIN = 110 MHz @ -9 dBFS While Channel B Digitizes fIN = 110 M z @ -9 dBFS
Figure 19. Single-Tone FFT of Channel B Digitizing fIN = 140 MHz @ -9 dBFS While Channel A Digitizes fIN = 140 MHz @ -9dBFS
0 -10 -20 -30
MAGNITUDE (dB)
1
-40 -50 -60 -70 -80 -90 -100
05154-026
2 3 6 4 5
-110 -120 -130 0 3.25 6.50
9.75 13.00 16.25 19.50 22.75 26.00 29.25 32.50 FREQUENCY (MHz)
Figure 17. Single-Tone FFT of Channel B Digitizing fIN = 110 MHz @ -9 dBFS While Channel A Digitizes fIN = 110 MHz @ -9 dBFS
Rev. 0 | Page 10 of 20
05154-022
-110
AD15252 THEORY OF OPERATION
The AD15252 consists of two high performance ADC channels. The dual ADC paths are independent, except for a shared internal band gap reference source, VREF. Each path consists of a differential front end amplification circuit followed by a sample-and-hold amplifier and multistage pipeline ADC. The output-staging block aligns the data, carries out the error correction, and passes the data to the output buffers. The output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given full-scale input frequency (fINPUT) due only to aperture jitter (tJ) can be calculated by SNR Degradation = 20 x log 10 (1/2 x p x f INPUT x tJ) In the equation, the rms aperture jitter, tJ, represents the rootsum square of all jitter sources, which includes the clock input, analog input signal, and ADC aperture jitter specification. Undersampling applications are particularly sensitive to jitter. For optimal performance, especially in cases where aperture jitter can affect the dynamic range of the AD15252, it is important to minimize input clock jitter. The clock input circuitry should use stable references, for example, using analog power and ground planes to generate the valid high and low digital levels for the AD15252 clock input. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step.
ANALOG INPUT
Each analog input is fully differential, allowing sampling of differential input signals. The differential input signals are accoupled and terminated in 100 input impedances. The fullscale differential signal input range is 296 mV p-p.
VOLTAGE REFERENCE
The internal voltage reference of the ADC is pin strapped to a fixed value of 0.5 V. A 10 F capacitor should be used between REFT and REFB.
CLOCK INPUT AND CONSIDERATIONS
Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and, as a result, can be sensitive to clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD15252 provides separate clock inputs for each channel. The optimum performance is achieved with the clocks operated at the same frequency and phase. Clocking the channels asynchronously can significantly degrade performance. In some applications, it is desirable to skew the clock timing of adjacent channels. The AD15252's separate clock inputs allow clock timing skew (typically 1 ns) between the channels without significant performance degradation. The AD15252 contains two internal clock duty cycle stabilizers (DCS), one for each converter, which retime the nonsampling edge, providing an internal clock with a nominal 50% duty cycle. Input clock rates of over 40 MHz can use the DCS so that a wide range of input clock duty cycles can be accommodated. Maintaining a 50% duty cycle clock is particularly important in high speed applications, when proper track-and-hold times for the converter are required to maintain high performance. The duty cycle stabilizer uses a delay-locked loop to create the nonsampling edge. As a result, any change to the sampling frequency requires approximately 2 s to 3 s to allow the DLL to acquire and settle to the new rate.
POWER DISSIPATION AND STANDBY MODE
The power dissipated by the AD15252 is proportional to its sampling rates. The digital (DRVDD) power dissipation is determined primarily by the strength of the digital drivers and the load on each output bit. The digital drive current can be calculated by IDRVDD = VDRVDD x CLOAD x fCLOCK x N where: N is the number of bits changing. CLOAD is the average load on the digital pins that changed. The analog circuitry is optimally biased so that each speed grade provides excellent performance while affording reduced power consumption. Each speed grade dissipates a baseline power at low sample rates that increase with clock frequency. Either channel of the AD15252 can be placed into standby mode independently by asserting the PDWN_A or PDWN_B pins. The minimum standby power is achieved when both channels are placed into full power-down mode using PDWN_A = PDWN_B = high. Under this condition, the internal references are powered down. When either or both of the channel paths are enabled after a power-down, the wake-up time is directly related to the recharging of the REFT and REFB decoupling capacitors and to the duration of the power-down. Typically, it takes approximately 5 ms to restore full operation with fully discharged 10 F decoupling capacitors on REFT and REFB.
Rev. 0 | Page 11 of 20
AD15252
A single channel can be powered down for moderate power savings. The powered-down channel shuts down internal circuits, but both the reference buffers and shared reference remain powered. Because the buffer and voltage reference remain powered, the wake-up time is reduced to several clock cycles. When using only one channel of the AD15252, the clock for the disabled channel should also be disabled, or distortion occurs in the channel in use. The data format can be selected for either offset binary or twos complement. This is discussed later in the Data Format section.
TIMING
The AD15252 provides latched data outputs with a pipeline delay of seven clock cycles. Data outputs are available one propagation delay (tPD) after the rising edge of the clock signal. Refer to Figure 20 for a detailed timing diagram. The length of the output data lines and the loads placed on them should be minimized to reduce transients within the AD15252. These transients can detract from the converter's dynamic performance. The lowest typical conversion rate of the AD15252 is 1 MSPS. At clock rates below 1 MSPS, dynamic performance can degrade.
DIGITAL OUTPUTS
The AD15252 output drivers can be configured to interface with 2.5 V or 3.3 V logic families by matching DRVDD to the digital supply of the interfaced logic. The output drivers are sized to provide sufficient output current to drive a wide variety of logic families. However, large drive currents tend to cause current glitches on the supplies, which can affect converter performance. Applications requiring the ADC to drive large capacitive loads or large fan-outs can require external buffers or latches.
DATA FORMAT
The AD15252 data output format can be configured for either twos complement or offset binary. This is controlled by the data format select pin (DFS). Connecting DFS to AGND produces offset binary output data. Conversely, connecting DFS to AVDD formats the output data as twos complement.
A-1
A0
A1
A2
A8 A3 A4 A5 A7 A6
ANALOG INPUT ADC A
B-1
B0
B1
B2
B8 B3 B4 B5 B7 B6
ANALOG INPUT ADC B
CLK_A = CLK_B = MUX_SELECT
B-8
A-7
B-7
A-6
B-6
A-5
B-5
A-4
B-4
A-3
B-3
A-2
B-2
A-1
B-1
A0
B0
A1
D0_A -D11_A
05154-002
tODF
tODR
Figure 20. Example of Multiplexed Data Format Using the Channel A Output and the Same Clock Tied to CLK_A, CLK_B, and MUX_SELECT
Rev. 0 | Page 12 of 20
AD15252 PCB AND EVALUATION BOARD
05154-027
Figure 21. AD15252 Evaluation Board Top Silk
Figure 23. AD15252 Evaluation Board Top Mask
05154-028
Figure 22. AD15252 Evaluation Board Top Paste
Figure 24. AD15252 Evaluation Board Top Signal
Rev. 0 | Page 13 of 20
05154-030
05154-029
AD15252
05154-031
Figure 25. AD15252 Evaluation Board Power Plane
Figure 27. AD15252 Evaluation Board Bottom Signal
05154-032
Figure 26. AD15252 Evaluation Board Ground Plane
Figure 28. AD15252 Evaluation Board Bottom Mask
Rev. 0 | Page 14 of 20
05154-034
05154-033
AD15252
Figure 29. AD15252 Evaluation Board Bottom Paste
Rev. 0 | Page 15 of 20
05154-035
AD15252
J6
AVDD +VCC DRVDD E1 E3 E5 E7 E9 E10 E8 E6 E4 E2 DGND DGND DGND DGND DGND DGND JP10 AVDD
1 2 1 2
JP9
1 2 3 4
+VDD DGND DRVDD DGND
+VDD
2 1 2
DIGITAL +2.5V +VCC AGND AGND + C7 10F C29 0.1F L2 AGND DGND AGND AGND DUTAVDD C1 0.1F AGND DUTAVDD C26 0.1F R7 0 VIN+A OTR_A A4 OTR_A R8 0 VIN-A VIN+A VIN-A VINA VINA VCM_A VREF
PRI AVDD AVDD AVDD AVDD AVDD AVDD DRVDD DRVDD C1 C2 C3 F1 F2 F3 E6 D6
ANALOG +3.3V DUTAVDD DRVDD DUTDRVDD +VDD
Z5.531.3425.0
1
J5
C28 10F C31 0.1F L3 AGND DGND L4 AGND C8 0.1F C20 0.1F AGND AGND
+ C30 10F C9 10F C2 10F
L1
+
+ C10 10F
+
+ C13 10F
+
+ C15 10F
1 2 3 4
+VCC AGND AVDD AGND
DGND
Z5.531.3425.0
E11 E12
DUTDVDD C27 0.1F DGND AGND
J1 Z = 50 O R11 100 OEB_A DUTCLK_A PDWN_A OEB_A CLK_A PDWN_A D4 B4 C4
T1
6
1
R1 DNI
PRI
SEC
ANALOG +3.3V
MSB_A
R81 5.1k PDWN_A JP1
4 3 TC1-1-13M
6 T2
AGND AGND
SEC 1
R96 DNI A1 A2 A3 D1 C3 10F D2 REF_RTN DFS DFS U1 E4 G4 F4 OEB_B CLK_B PDWN_B E3
TC1-1-13M 3 4
ANALOG +3.3V
PDWN_A
R6 5.1k OEB_A ANALOG +3.3V
PRI
6 T3
TC1-1-13M 3 4
1
SEC
AGND AGND AGND AGND AGND AGND AGND DRGND DRGND
05154-036
B1 B2 B3 D3 G1 G2 G3 D5 E5
Figure 30. AD15252 Evaluation Board Schematic: Analog Front End ADC
C23 0.1F AGND AGND
Rev. 0 | Page 16 of 20
AD15252
D11_A D10_A D09_A D08_A D07_A D06_A D05_A D04_A D03_A D02_A D01_A D00_A D11_A D10_A D09_A D08_A D07_A D06_A D05_A D04_A D03_A D02_A D01_A D00_A R9 0 VIN+B R10 0 VIN-B C24 0.1F AGND R97 DNI AGND R12 100 VIN+B VIN-B VINB VINB VCM_B REFT OEB_B DUTCLK_B PDWN_B OTR_B E8 OTR_B H1 H2 H3 E1 LSB1_A LSB0_A LSB1_B LSB0_B C4 10F E2 D7 D8 F5 H4 REFB DNC DNC DNC DNC D11_B D10_B D09_B D08_B D07_B D06_B D05_B D04_B D03_B D02_B D01_B D00_B E7 F8 F7 G8 F6 H8 G7 H7 G6 H6 G5 H5 D11_B D10_B D09_B D08_B D07_B D06_B D05_B D04_B D03_B D02_B D01_B D00_B AGND AGND DGND
JP2
C5 A5 B5 A6 B6 A7 B7 A8 C6 B8 C7 C8
OEB_A LSB_A
OEB_B R5 5.1k
JP3
SHUNT ON = GND OFF = +3.3V
J2 Z = 50 O
T4
MSB_B
6
1
ANALOG +3.3V R3 5.1k PDWN_B ANALOG +3.3V
OEB_B
R4 DNI
PRI
SEC
4 3 TC1-1-13M
JP4
AGND
PDWN_B
R2 5.1k DFS
JP5
DFS LSB_B
AGND
AD15252
U2 1 19 DATACLK_A OTR_A D06_A D07_A D08_A D09_A D10_A D11_A R13 R14 R20 R19 R18 R17 R16 R15 150 150 150 150 150 150 150 150 LSB0_AX LSB0_A LSB1_A D00_A D01_A D02_A D03_A D04_A D05_A R28 R27 R26 R25 R24 R23 R22 R21 DNI DNI 150 150 150 150 150 150 LSB1_AX 1 19 2 3 4 5 6 7 8 9 10 OE1 OE2 IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 GND U3 VCC O0 O1 O2 O3 O4 O5 O6 O7 DIGITAL C17 +2.5V 0.1F 20 DGND 18 17 16 15 14 13 12 11 2 3 4 5 6 7 8 9 10 OE1 OE2 IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 GND VCC O0 O1 O2 O3 O4 O5 O6 O7 DIGITAL +2.5V 20 18 17 16 15 14 13 12 11 C16 0.1F DGND
R45 R46 R52 R51 R50 R49 R48 R47
22.1 22.1 22.1 22.1 22.1 22.1 22.1 22.1
DATACLK_A2 OTR_A2 D06_A2 D07_A2 D08_A2 D09_A2 D10_A2 D11_A2
74VHC541MTC
R60 R59 R58 R57 R56 R55 R54 R53
22.1 22.1 22.1 22.1 22.1 22.1 22.1 22.1
LSB0_A2 LSB1_A2 D00_A2 D01_A2 D02_A2 D03_A2 D04_A2 D05_A2 TP5
DGND DATACLK_A2 DGND D11_A2 D10_A2 D09_A2 D08_A2 D07_A2 D06_A2 D05_A2 D04_A2 D03_A2 D02_A2 D01_A2 D00_A2 LSB1_A2 LSB0_A2 OTR_A2 DGND
TSW-140-08-S-D-RA 79 77 75 73 71 69 67 65 63 61 59 57 55 53 51 49 47 45 43 41 J7:C DGND
TSW-140-08-S-D-RA 80 78 76 74 72 70 68 66 64 62 60 58 56 54 52 50 48 46 44 42 J7:D
74VHC541MTC DIGITAL +2.5V 20 18 17 16 15 14 13 12 11
U4 1 19 D05_B D06_B D07_B D08_B D09_B D10_B D11_B OTR_B R36 R35 R34 R33 R32 R31 R30 R29 150 150 150 150 150 150 150 150 LSB0_AX LSB1_B D00_B D01_B D02_B D03_B D04_B LSB0_B DATACLK_B R42 R41 R40 R39 R38 R37 R43 R44 DNI 150 150 150 150 150 DNI 0 LSB1_AX DGND 1 19 2 3 4 5 6 7 8 9 10 OE1 OE2 IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 GND U5 VCC O0 O1 O2 O3 O4 O5 O6 O7 2 3 4 5 6 7 8 9 10 OE1 OE2 IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 GND VCC O0 O1 O2 O3 O4 O5 O6 O7
C22 0.1F DGND
R68 R67 R66 R65 R64 R63 R62 R61
22.1 22.1 22.1 22.1 22.1 22.1 22.1 22.1
DATACLK_B2 OTR_B2 D06_B2 D07_B2 D08_B2 D09_B2 D10_B2 D11_B2
74VHC541MTC
DIGITAL C25 +2.5V 0.1F 20 DGND 18 17 16 15 14 13 12 11
DGND DATACLK_B2 DGND D11_B2 D10_B2 D09_B2 D08_B2 D07_B2 D06_B2 D05_B2 D04_B2 D03_B2 D02_B2 D01_B2 D00_B2 LSB1_B2 LSB0_B2 OTR_B2 DGND
TSW-140-08-S-D-RA 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 J7:A DGND
TSW-140-08-S-D-RA 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 J7:B
R74 R73 R72 R71 R70 R69 R75 R76
22.1 22.1 22.1 22.1 22.1 22.1 22.1 22.1
LSB0_B2 LSB1_B2 D00_B2 D01_B2 D02_B2 D03_B2 D04_B2 D05_B2 TP6
LSB1_AX R77 0
LSB0_AX R78 0
DGND LSB1_BX R79 0 LSB0_BX R80 0
05154-037
74VHC541MTC
DGND
Figure 31. AD15252 Evaluation Board Schematic: Digital Outputs
Rev. 0 | Page 17 of 20
AD15252
5 U6:C 6 U6:D 9 8
74VHC04MTC
74VHC04MTC
AGND
ANALOG +3.3V C11 0.1F
CLK_A 3 AGND
U6:B 4
U6:E 11 10
74VHC04MTC
TP7 JP6 R93 A 22.1 B
DUTCLK_A
74VHC04MTC
J3
C5 0.1F R83 49.9 AGND
R90 100k R94 0 R98 100k AGND 1 R82 DNI
ANALOG +3.3V C18 0.1F AGND U6:A VCC 2 GND 7 AGND 14
DATACLK_A DELAY A = 1 DELAY B = 2 DELAY
ANALOG +3.3V
U6:F 13 12
R85 0
R92 DNI
AGND DUTCLK_A
C14 0.1F
JP8
A B
1 7
Y1 14 8
C21 0.1F
74VHC04MTC 74VHC04MTC
TP8 DATACLK_A
AGND XTAL A = ENABLE B = DISABLE
VF140SHHL-65MHz ANALOG +3.3V C12 0.1F AGND AGND J4 C6 0.1F R84 49.9 AGND R100 1k R82 0 14 1 VCC GND R99 1k AGND JP7 R95 TP10 DNI A B 7 U7:A 2 U7:F 12 R87 DNI R91 DNI ANALOG +3.3V C19 0.1F R88 0
R89 0 DATACLK_B TP9
13
DUTCLK_B
74VHC04MTC 74VHC04MTC
AGND
CLK_B
3
U7:B 4
U7:E 11 10
74VHC04MTC
DUTCLK_B
74VHC04MTC
DATACLK_B DELAY A = 1 DELAY B = 2 DELAY U7:C 6 U7:D 9 8
74VHC04MTC
5
74VHC04MTC
AGND
Figure 32. AD15252 Evaluation Board Schematic: Encode
Rev. 0 | Page 18 of 20
05154-038
AD15252 OUTLINE DIMENSIONS
8.10 8.00 SQ 7.90
8 7 6 5 4 3 2 1 A
BALL A1 CORNER TOP VIEW
B
5.60 BSC SQ 0.80 BSC
C D E F G H
BOTTOM VIEW 1.70 1.55 1.35 DETAIL A
DETAIL A
0.34 NOM 0.25 MIN 0.55 0.50 0.45 BALL DIAMETER
1.31 1.21 1.10 COPLANARITY 0.12
SEATING PLANE
COMPLIANT TO JEDEC STANDARDS MO-205-BA
Figure 33. 64-Lead Chip Scale Package Ball Grid Array [CSP_BGA] (BC-64-1) Dimensions shown in millimeters
ORDERING GUIDE
Model AD15252BBC AD15252/PCB Temperature Range -40C to +85C Package Description 64-Lead Chip Scale Package Ball Grid Array (CSP_BGA) Evaluation Board Package Option BC-64-1
Rev. 0 | Page 19 of 20
AD15252 NOTES
(c) 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05154-0-8/05(0)
Rev. 0 | Page 20 of 20

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